Build Semiconductor Chips with AI

This session explores how AI can be integrated into the semiconductor chip design loop, addressing challenges such as macro placement, congestion, and timing. Presented by Lossfunk and hosted by Team Lossfunk, the event features speakers Hariharan Ayappane and Naveen Venkat from Archgen AI, whose chip-design engine recently won the HRT and Partcl macro-placement challenge. The talk will cover AI-driven proposal generation, incremental scoring, and congestion-aware repair. The event takes place i